A common configuration for integrated circuits that perform binary signal processing functions is illustrated in FIG. 1, wherein integrated circuit chip 10 is illustrated as including core 12 containing the main logic area where the binary signal processing functions are performed. Signals are coupled from and into core 12 via N identical general purpose input/output pads 14, each connected to one of N input/output pins 16, where N is an integer greater than 1 and typically has a value of 16, 32, or more. Pads 14 are at the periphery of the chip and connected via appropriate bonded leads to pins 16 fixedly connected at the outer edges of a package (not shown) containing the chip. Since all of pads 14 are identical, the description proceeds with regard to a single pad 14.
General purpose input/output pad 14 includes terminal 18 directly connected to pin 16. Terminal 18 is connected to a DC reference voltage at terminal 20 by device 22, which can be either a pullup or pulldown device; for ease of further description, it is assumed that device 22 is a pullup device which, when enabled, tends to maintain terminal 18 at the positive DC voltage at terminal 20. When pullup device 22 is disabled, terminal 18 is free to float and the voltage at terminal 18 is controlled by (1) the voltage supplied to the terminal from pin 16 when a signal is coupled to integrated circuit chip 10 via pin 16 or (2) the voltage at the output of amplifier 24. Pullup device 22, when enabled, has a much greater impedance than the output impedance of amplifier 24 or of the signal source external to chip 10, so the amplifier or the external source can overcome the pullup effects of device 22. When a voltage is supplied to terminal 18 from pin 16, the voltage at terminal 18 is coupled to the input of amplifier 26, having an output coupled to circuitry within core 12.
Core 12 includes addressable register 28 having three memory elements 30, 32 and 34 for each of the N general purpose input/output pads 14. Other portions of core 12 load binary signal levels into memory elements 30, 32 and 34. Memory element 30 stores a binary control signal level indicative of whether pullup device 22 is enabled to couple the voltage at terminal 20 to terminal 18 or if pullup device 22 is to be disabled, in which case terminal 18 can float or is driven to a voltage at an output of a source supplying a signal to terminal 18. Memory element 32 is loaded with a binary value indicative of whether input/output pad 14 is to supply a binary 1 or 0 value to pin 16. In the logic set of the prior art discussed in connection with FIG. 1 and the preferred embodiment of the present invention as described in connection with the remaining figures, binary 1 and 0 values in element 34 are respectively associated with low (ground) and positive (high) voltages, but it is to be understood that other logic sets can be used. (The binary 1 and 0 values of other binary signals are respectively associated with positive high and low (ground) voltages.) The value in storage element 32 is selectively coupled through amplifier 24 to terminal 18 under the control of binary values loaded in memory element 34. To this end, the signal in element 34 is supplied to inverting power supply terminal 36 of tristate amplifier 24 so that when the signal in element 34 has a low voltage (associated with a binary 1 value) the amplifier is enabled and has a low output impedance serving as a voltage source for a positive (binary 0 value) voltage and a low (binary 1 value) voltage determined by the binary value of the signal in element 32. When a binary 3 is in element 34, element 30 is usually loaded with a binary 0 to disable pullup device 22. When a binary 0 is in element 34, amplifier 24 is disabled, has a high output impedance and an output voltage that is independent of the binary signal in element 32.
with this prior art arrangement, the signals in storage elements 30 and 34 both have binary 0 values to disable pullup device 22 and amplifier 24 when a signal is supplied to pin 16 from circuitry external to integrated circuit 10 so the voltage at terminal 18 is equal to the voltage supplied to it from external circuitry via pin 16. In addition, pullup device 22 may be enabled for some types of input to pin 16 from external sources, e.g., (1) if an external switch is tied to ground, (2) if an external signal is derived by an open drain device, and (3) if no source is connected to the pin, so the pin would otherwise float. When amplifier 24 is disabled by the high voltage in storage element 34 and no signal is to be applied to pin 16 from external circuitry, terminal 18 is maintained at the voltage of terminal 20 by enabling, i.e. activating, pullup device 22 by a high voltage (binary 1 value) in storage element 30.
While the prior art device functions adequately, we have realized that the prior art has the disadvantage of requiring an excess lead wire. We have realized it is not necessary to provide a separate lead wire from storage element 30 to pullup device 22 and that storage element 30 can be eliminated for each input/output pad 14. Since register 28 is usually buried deep in core 12, elimination of the lead wire and of .storage element 30 decreases the size of core 12 and therefore of the entire integrated circuit chip 20. Elimination of these parts is significant when it is realized there are frequently 32 or more input/output pads.
we have also realized current and therefore power consumption can be reduced by decreasing the current supplied via the pullup devices during certain operating conditions of the core, particularly for a low power, i.e. sleep, mode of operation of the integrated circuit chip and/or when the integrated circuit chip is responsive to an externally derived interrupt signal.
It is, accordingly, an object of the present invention to provide a new and improved integrated circuit chip having a core for performing binary signal processing functions as well as general purpose input/output pads, wherein the volumetric requirements of the integrated circuit chip are reduced.
An additional object of the invention is to provide a new and improved integrated circuit chip including a core for performing binary signal processing functions in combination with a general purpose input/output pad having a pullup or pulldown device that is controlled by the same signals that control other components in the input/output pad so as to reduce the number of leads between the core and the input/output pad.
An additional object of the invention is to provide a new and improved integrated circuit having input/output pads including pullup or pulldown devices that are operated at relatively low current levels when the integrated circuit is operated under certain operating conditions, e.g. low power (sleep) and/or interrupt conditions.